Active devices such as transistors have been routinely used by circuit designers as current sources. From circuit theory, it is known that a current source provides constant current independent of the voltage applied across the device. Both bipolar and FET field effect transistors have been used as current sources with equal success.
A typical integrated circuit current source has been described by Lachmann et al. in the U.S. Pat. No. 4,651,083, wherein a constant current output is obtained by having an operational amplifier with an inverting input to which a reference voltage is attached; a first stage to which the output is coupled to and by which the output voltage of the operational amplifier is converted into a first current; and a second stage coupled to the output of the operational amplifier for converting the output voltage of the operational amplifier to a second current, providing an output current which is essentially constant to a first approximation, and additional stages provided with a current mirror for outputting constant current over a wide region of voltages. Whereas Lachmann describes a circuit having feedback, it is limited to only bipolar devices, and cannot be implemented with FET devices.
Whereas the characteristics of an ideal current source can be achieved with standard transistors, several practical problems are known to introduce severe limitations that seriously affect the performance of the FET and, consequently, of the current source. Two of the main reasons of these limitations are: the voltage operating range and the output resistance of the FET current source.
Some of the limitations imposed by the aforementioned problems were found during the design of an IEEE 1394 Phy Chip which requires several current sources. This chip, well known to practitioners of the art, is a serial implementation of a parallel SCSI (Small Computer System Interface, i.e., a standardized peripheral interconnection scheme) I/O bus. IEEE Standard 1394 specifies interface levels for a 5 volt power supply, (wherein an interface includes drivers, receivers, low level protocols, and the like). A 1394 chip typically uses current mode signalling such that the current sources generate fixed currents that are driven across terminators to create appropriate voltage levels. The direction of the current through the terminators switches back and forth to create equal and opposite differential terminator voltages used for a first mode of signalling. Additionally, the terminals are connected to a variable voltage supply that switches between two levels to vary the signals common mode voltage. This common mode voltage is used as a second signalling mode.
It is common practice for many chip implementations to use a 3.3 volt CMOS technology of any circuit or chip, of which the Phy chip is one example, to reduce power consumption. The use of 3.3 volt technology to generate interface levels for a 5 volt interface creates a need for a current source that operates having a low voltage drop across it. The reduced voltage overhead (i.e., 3.3 volts when compared to the 5 volts) along with P1394 specification tolerances forces the current source to operate with as little as 50 millivolts across it. While investigating one such current source, the required operating Vsd across the current source FET was found to be so small, such that the resulting FET would have been prohibitive in its required size. Thus, using prior current sources, the design of the entire Phy Chip would have been unfeasible.
To gain a better understanding of the problem caused by the limitations, reference is made to FIG. 1 showing typical I-V characteristics of a typical FET, in this case a pFET, wherein the Source to Drain Current Isd is plotted against the Source to Drain Voltage Vsd. For optimum performance the transistor is to remain in the saturation region, i.e., to the right of the parabola defined by Vsd=Vsg-Vt. The FET acts as a current source in the "flat" section of the output characteristics, wherein Isd remains essentially constant over large variations of Vsd. Practitioners of the art will fully appreciate that below saturation, a current source loses its effectiveness. While the current Isd remains flat in the saturation region, in the linear region to the left of the parabola, the FET acts as a resistor so that highly non-linear voltage variations distort the operation of the FET as a current source. Moreover, at higher current levels, the linear region is even larger, thereby limiting the operating region of the current source even further.
The severe voltage range limitation of an FET operating in its linear region will be better understood in terms of the following discussion.
Normally, a current source, particularly, one implemented with FET devices, is designed based on two criteria: the current Ids and the minimum Vsd voltage level. Assuming a preferred minimum Vsd=110 mv and a current level I=4 mA, the width W to length 1 ratio of the device can be computed as follows: EQU S=2*I/(k'*Vsd+Vsd)=W/1,
wherein S=CMOS ratio (which is commonly obtained from any CMOS Design Manual), W=device width in .mu.m, and L=device length in .mu.m. By way of example: EQU S=2*4,000/(24*0.1*0.1)=33,333.
Additionally, to eliminate short channel modulation phenomena (represented by the slope of the curve of the current in the saturation region, when plotting the characteristic curves of an FET device), which detracts from the independence of Isd vs. Vsd, the transistor length become relatively large. Simulation runs indicate that a channel length of 4 .mu.m. for a typical CMOS device provides adequate control of the channel modulation term (i.e., a modifier to the drain current of an FET device, which is a function of the physical parameters of the device). The resultant width W is: EQU W=S*L=3333*4 .mu.m=133,333 .mu.m.
Such a large FET is clearly unacceptable. From the aforementioned discussion, it is evident that the width becomes prohibitive due to the area consumed by the device, in addition to introducing unacceptable diffusion and gate capacitances.
FIG. 2 is a schematic diagram showing how to perform a prior art current measurement in series with the output of an FET. As previously stated, it is advantageous to operate the FET device in its linear region while still being able to maintain a constant current at the output node even in the presence of large variations of Vsd, since the current source can be made to operate using a small Vsd. The diagram shows a compensating setup that allows the FET to generate a constant current at its output, independent of the output node voltage or any load attached to it. Thus, conceptually, by placing an ammeter in series with the output node, a control setup could be configured to detect the amount of current flowing in or out of the output node and somehow restore it to its original current value. A negative feedback control setup can thus be used to achieve this goal.
Although the conceptual representation of the such a setup is theoretically simple and straight forward, its actual implementation is far from trivial. The main drawback resides in the manner of measuring current which usually produces a significant voltage drop across the measuring element. By way of example, a typical ammeter utilizes precision resistors, across which a voltage is measured. The additional resistor in series with the FET device further reduces the available voltage Vsd by a finite amount, essentially limiting the voltage from use where it is most needed, namely, across the load. Thus, an improved method for dynamically measuring the output current without inserting in series any component capable of affecting the output voltage is needed.